(1) Field of the Invention
The present invention relates to a structure and production method of a multi-layer printed-wiring board produced by a so-called buildup process which comprises the steps of: forming a first conductive layer providing electric conductivity on one or both sides of an insulating substrate providing electrical insulation; forming another insulating layer providing electrical insulation at specific sites on the first conductive layer (e.g., a through-hole); and covering the insulating layer with another conductive layer providing electric conductivity.
(2) Description of the Prior Art
So-called conventional buildup type printed-wiring boards which are formed by providing insulating layers and/or conductive layers on a previously formed, layered printed-wiring board have been well known.
However, the well-known buildup configuration is a general one and does not include the techniques such as the so-called chip-on-hole.
The chip-on-hole technique is to produce a printed-wiring board which is formed by plating with copper etc., on a through-hole, or so-called inner via-hole for connecting only between the layers, and coating with solder or the like on the plating.
This method allows chip components to be mounted on a solder paste etc. which has been printed on the plating for plugging holes. In other words, it is impossible to mount a chip component on a through-hole unless the through-hole is plugged up by plating.
As seen in the above, a printed-wiring board formed by using the chip-on-hole technique has reduced its substrate size compared to a printed-wiring board which has the same functionality but was formed by other than the chip-on-hole technique. In other words, if the equally sized print-wiring board is produced, the print-wiring board using the chip-on-hole technique can be improved more in its functionality than the printed-wiring board which was formed by other than the chip-on-hole technique. Briefly, the printed-wiring board using the chip-on-hole technique is one which can make the product compact and light-weight.
The production method of a buildup multi-layer printed-wiring board of such a chip-on-hole makeup will be described with reference to FIGS. 1 through 7.
As the substrate, an insulating plate 51 with copper foils 52, 52 applied on both sides thereof is prepared (cf. FIG. 1). Insulating plate 51 is usually 0.1-1.6 mm in thickness and is made from glass epoxy resin, in general. The thickness of copper foil 52 is generally 9-18 .mu.m.
Next, a double-sided printed-wiring board is produced by a general copper through-hole tenting technique. FIG.2 shows the double-sided printed-wiring board thus produced. In this figure, reference numerals 53 and 54 designate through-holes both being provided with copper plate 55 therein. The thickness of copper plate 55 is appropriately 15-20 .mu.m.
Through-hole 53 is an ordinary one which has both the functions of signal communication and mounting a discreet part. Through-hole 54 is one which is dedicatedly used for signal communication. Therefore, the inside diameter of through-hole 54 is not limited in size and can be designed as small as possible, whereas the inside diameter of through hole 53 is limited as to its minimum size by the size of the lead of the discreet part.
Reference numerals 56 and 57 in the figure designate a solder resist and a conductive portion, respectively.
Next, in order to form an insulating resin layer over through-hole 54 in the thus completed double-sided printed-wiring board, an insulating layer 58 is formed by printing or a film deposition process. Insulating layer 58 is formed not only directly above through-hole 54 but also is formed so as to cover a peripheral portion thereof. As required, the resin applied is cured (see FIG. 3).
Next, insulating layer 58 thus formed is covered with an electroless copper plating 59 overlapping thereon. Areas which should not be subjected to the process for electroless copper plating 59 are provided with a plating resist (not shown) before the step, and then the plating resist is peeled off after the completion of electroless copper plating 59 (see FIG. 4). In this way, a buildup printed-wiring board is finished.
Then, a mounting step of chip parts is effected. Illustratively, solder paste 60 is printed on electroless copper plating 59 formed on through-hole 54 (see FIG. 5). Next, a chip part (not shown) is tacked on solder paste 60, then solder paste 60 is re-fused by solder-reflow to thereby mount the chip part on electroless copper plate 59.
The multi-layer printed-wiring plate of a buildup type thus produced can be manufactured at a low cost in a short period of time, and has no need to use a glass cloth as a connecting means, which was needed in the conventional multi-layer printed-wiring board using prepleg, and also has incidental effects such as excellent high-frequency characteristics.
However, the multi-layer printed-wiring board configured as above, has suffered from a problem of lack of smoothness on the surface of electroless copper plating 59, as is seen in FIG. 5. More clearly, as shown in an enlarged view in FIG. 6, the surface of electroless copper plating 59 has hollows or craters, presenting poor smoothness.
Primarily, the object of forming a plating layer (electroless copper plating 59) as a `footing` on through-hole 54 only for communication of electric signals is to mount a chip part on the plating layer. Therefore, the plating layer poor in smoothness, directly results in poor stability of the chip part mounted thereon.
In practice, a chip part is rarely mounted directly on the plating layer; in most cases chip parts are mounted after providing solder paste 60 by printing or other methods and the providing them to be soldered by solder reflow, so that lack of the smoothness in the plating layer will not bring about direct instability in the connection of the chip parts.
Still, the printing process can be more easily performed if the surface to be printed with solder paste 60, that is, the surface of electroless copper plate 59 is of a greater smoothness. Also, the bonding stability of the chip part after solder reflow will be enhanced. In particular, with the evolution of chip parts to greater compactness, such as the appearance of a 1005 type (i.e., a chip part having a size of 1.0 mm .times.0.5 mm), it is easily conceived that the smoothness of the printing surface on which the solder paste should be printed largely affects the connection stability of chip parts.
Products having printed-wiring boards which were prepared by these steps are often mishandled. For example, the products often encounter mechanical impacts such as being dropped or being struck.
Now, FIG. 7 is an enlarged view showing a state after a soldering process, where a chip part is mounted on a printed-wiring board. Solder paste 60 does not bond chip part 61 throughout the underside thereof but bonds it at the ends only. In some cases, the contact area is smaller than the above; the chip part may be bonded at one end thereof, as seen in the figure.
If products with chip parts bonded in this manner are dropped or struck, mechanical stress concentrates on this small bonded portion and thereby breaks it down, resulting in reduction of the reliability of the product.